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a67l06181/A67L93361 1m x 18, 512k x 36 lvttl, flow-through zebl tm sram (march, 2008, version 1.0) amic technology, corp. document title 1m x 18, 512k x 36 lvttl, flow-through zebl tm sram revision history rev. no. history issue date remark 0.0 initial issue august, 20, 2005 preliminary 0.1 modify dc specification to exact value march 2, 2006 modify speed specification from cycle time to access time 1.0 final version release march 10, 2008
a67l06181/A67L93361 1m x 18, 512k x 36 lvttl, flow-through zebl tm sram (march, 2008, version 1.0) 2 amic technology, corp. features ? fast access time: 6.5/7.5/8.5 ns (153, 133, 117 mhz) ? zero bus latency between read and write cycles allows 100% bus utilization ? signal +3.3v 5% power supply ? individual byte write control capability ? clock enable ( cen ) pin to enable clock and suspend operations ? clock-controlled and regi stered address, data and control signals ? registered output for pipelined applications ? three separate chip enables allow wide range of options for ce control, address pipelining ? internally self-timed write cycle ? selectable burst mode (linear or interleaved) ? sleep mode (zz pin) provided ? available in 100 pin lqfp package ? industrial operating te mperature range: -25 c to +85 c for ?i series ? all pb-free (lead-free) pr oducts are rohs compliant general description the amic zero bus latency (zebl tm ) sram family employs high-speed, low-power cmos designs using an advanced cmos process. the a67l06181, A67L93361 srams in tegrate a 1m x 18, 512k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bi t burst counter. these srams are optimized for 100 percent bus utilization without the insertion of any wait cycles during write-read alternation. the positive edge triggered single clock input (clk) controls all synchronous inputs passing through the registers. the synchronous i nputs include all address, all data inputs, active low chip enable ( ce ), two additional chip enables for easy depth expansion (ce2, ce2 ), cycle start input (adv/ ld ), synchronous clock enable ( cen ), byte write enables ( bw1 , bw2 , bw3 , bw4 ) and read/write (r/ w ). asynchronous inputs in clude the output enable ( oe ), clock (clk), sleep mode (zz, ti ed low if unused) and burst mode (mode). burst mode can provide either interleaved or linear operation, burst oper ation can be initiated by synchronous address advance/load (adv/ ld ) pin in low state. subsequent burst address can be internally generated by the chip and contro lled by the same input pin adv/ ld in high state. write cycles are internally self-time and synchronous with the rising edge of the clock input and when r/ w is low. the feature simplified the writ e interface. individual byte enables allow individual bytes to be written. bw1 controls i/oa pins; bw2 controls i/ob pins; bw3 controls i/oc pins; and bw4 controls i/od pins. cycle types can only be defined when an address is loaded. the sram operates from a +3.3v power supply, and all inputs and outputs are lvttl-c ompatible. the device is ideally suited for high bandwidth utilization systems.
a67l06181/A67L93361 (march, 2008, version 1.0) 3 amic technology, corp. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 a17 a16 a15 a14 a13 a12 a11 nc vcc vss nc nc a0 a1 a2 a3 a4 a5 mode 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1m x 18 a16 a15 a14 a13 a12 a11 a10 vcc vss nc a0 a1 a2 a3 a4 a5 mode 512k x 36 i/ob 8 i/oa 8 nc nc a6 a7 ce2 nc nc vcc vss clk a19 a18 a8 a9 a10 nc nc vccq vssq nc vssq vccq vss vss vcc zz vccq vssq nc nc vssq vccq nc nc nc i/oa 0 i/oa 1 nc nc nc vccq vssq nc nc vssq vccq vss vcc vss vccq vssq nc vssq vccq nc nc nc i/ob 8 i/ob 7 i/ob 6 vcc i/ob 4 ce2 a7 a6 clk vss vcc a9 a8 a18 a17 vccq vssq vssq vccq vss vss vcc zz vccq vssq vssq vccq i/ob 7 ce ce bw4 bw3 bw2 bw2 bw1 bw1 ce2 ce2 cen cen oe oe adv/ ld adv/ ld a67l06181e A67L93361e r/w r/w i/ob 5 i/ob 3 i/ob 2 i/ob 1 vccq vssq vssq vccq vcc vcc vss vccq vssq vssq vccq vss i/oc 0 i/oc 1 i/oc 2 i/oc 3 i/oc 4 i/oc 5 i/oc 6 i/oc 7 i/od 0 i/od 1 i/od 2 i/od 3 i/od 4 i/od 5 i/od 6 i/od 7 i/od 8 i/oa 2 i/oa 3 i/oa 4 i/oa 5 i/oa 6 i/oa 7 i/oa 8 i/ob 6 i/ob 5 i/ob 4 i/ob 3 i/ob 2 i/ob 1 i/ob 0 i/oa 7 i/oa 6 i/oa 5 i/oa 4 i/oa 3 i/oa 2 i/oa 1 i/oa 0 i/oc 8 i/ob 0 nc nc
a67l06181/A67L93361 (march, 2008, version 1.0) 4 amic technology, corp. block diagram (512k x 36) mode logic clk logic address registers burst logic address counter clr write registry & control logic bytea write driver byteb write driver bytec write driver byted write driver 9 9 9 9 512kx9x4 memory array 9 9 9 9 output buffers chip enable logic flow-through enable logic output enable logic zz mode adv/ld clk a0-a18 r/w bw1 bw2 bw3 bw4 ce ce2 ce2 oe cen write address register adv/ld data-in registers i/o s sense amps
a67l06181/A67L93361 (march, 2008, version 1.0) 5 amic technology, corp. block diagram (1m x 18) data-in registers mode logic clk logic address registers burst logic address counter clr write registry & control logic bytea write driver byteb write driver 9 9 1mx9x2 memory array 9 9 output buffers chip enable logic flow- through enable logic output enable logic zz mode adv/ld clk a0- a19 r/w bw1 bw2 ce ce2 ce2 oe cen write address register adv/ld i/o s sense amps
a67l06181/A67L93361 (march, 2008, version 1.0) 6 amic technology, corp. pin description pin no. symbol description lqfp (x18) lqfp (x36) 37 36 35,34,33,32, 100,99,82,81 44,45,46,47, 48,49,50,83 84 80 37 36 35,34,33,32, 100,99,82,81 45,46,47,48, 49,50,83,84 44 a0 a1 a2 ? a9 a11-a18 a19 a10 synchronous address inputs : t hese inputs are registered and must meet the setup and hold times around the rising edge of clk. pins 83 and 84 are reserved as address bits for higher-density 9mb and 18mb dba srams, respectively. a0 and a1 are the two lest significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 93 ( bw1 ) 94 ( bw2 ) 93 ( bw1 ) 94 ( bw2 ) 95 ( bw3 ) 96 ( bw4 ) bw1 bw2 bw3 bw4 synchronous byte write enables : these active low inputs allow individual bytes to be written when a write cycle is active and must meet the setup and hold times around the rising edge of clk. byte writes need to be asserted on the same cycle as the address, bws are associated with addresses and apply to subsequent data. bw1 controls i/oa pins; bw2 controls i/ob pins; bw3 controls i/oc pins; bw4 controls i/od pins. 89 89 clk clock : this signal registers t he address, data, chip enables, byte write enables and burst c ontrol inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 98 98 ce synchronous chip enable : this active low input is used to enable the device. this input is sampled only when a new external address is loaded (adv/ ld low). 92 92 ce2 synchronous chip enable : this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ ld low). this input can be used for memory depth expansion. 97 97 ce2 synchronous chip enable : this active high input is used to enable the device and is sampled only when a new external address is loaded (adv/ ld low). this input can be used for memory depth expansion. 86 86 oe output enable : this active low asynchronous input enables the data i/o output drivers. 85 85 adv/ ld synchronous address advance/load : when high, this input is used to advance t he internal burst counter, controlling burst access after the external address is loaded. when high, r/ w is ignored. a low on this pin permits a new address to be loaded at clk rising edge. 87 87 cen synchronous clock enable : this active low input permits clk to propagate throughout the device. when high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk.
a67l06181/A67L93361 (march, 2008, version 1.0) 7 amic technology, corp. pin description (continued) pin no. symbol description lqfp (x18) lqfp (x36) 64 64 zz snooze enable : this active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when active, all other inputs are ignored. 88 88 r/ w read/write : this active input determines the cycle type when adv/ ld is low. this is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus width writes occur if all byte write enables are low. 74, 73, 72, 69, 68 63, 62, 59, 58 24, 23, 22, 19, 18 13, 12, 9, 8 52, 53, 56, 57, 58, 59, 62, 63, 51 68, 69, 72, 73, 74, 75, 78, 79, 80 2, 3, 6, 7, 8, 9, 12, 13,1 18, 19, 22, 23, 24, 25, 28, 29, 30 i/oa i/ob i/oc i/od sram data i/o : byte ?a? is i/oa pins; byte ?b? is i/ob pins; byte ?c? is i/oc pins; byte ?d? is i/od pins. input data must meet setup and hold times around clk rising edge. 31 31 mode mode: this input selects the burst sequence. a low on this pin selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42,43 51, 52, 53, 56, 57, 75, 78, 79, 95, 96 38,39,42,43 nc no connect : these pins can be left floating or connected to gnd to minimize thermal impedance. 15, 16, 41, 65, 91 15, 16, 41, 65, 91 vcc power supply 4, 11, 20, 27, 54, 61, 70, 77 4, 11, 20, 27, 54, 61, 70, 77 vccq isolated output buffer supply 14, 17, 40, 66, 67, 90 14, 17, 40, 66, 67, 90 vss ground : gnd. 5,10,21,26, 55,60,71,76 5,10,21,26, 55,60,71,76 vssq isolated output buffer ground
a67l06181/A67L93361 (march, 2008, version 1.0) 8 amic technology, corp. truth table (notes 5 - 7) operation address used ce ce2 ce2 zz adv/ ld r/ w bwx oe cen clk i/o notes deselected cycle, power-down none h x x l l x x x l l h high-z deselected cycle, power-down none x h x l l x x x l l h high-z deselected cycle, power-down none x x l l l x x x l l h high-z continue deselect cycle none x x x l h x x x l l h high-z 1 read cycle (begin burst) external l l h l l h x l l l h q read cycle (continue burst) next x x x l h x x l l l h q 1,7 nop/dummy read (begin burst) external l l h l l h x h l l h high-z 2 dummy read (continue burst) next x x x l h x x h l l h high-z 1,2,7 write cycle (begin burst) external l l h l l l l x l l h d 3 write cycle (continue burst) next x x x l h x l x l l h d 1,3,7 nop/write abort (begin burst) none l l h l l l h x l l h high-z 2,3 write abort (continue burst) next x x x l h x h x l l h high-z 1,2,3,7 ignore clock edge (stall) current x x x l x x x x h l h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs. the type of cycle performed (read or write) is chosen in the initial begin burst cycle. a conti nue deselect cycle can only be entered if a deselect cycle is executed first. 2. dummy read and write abort cycles can be consider ed nops because the device per forms no operation. a write abort means a write command is giv en, but no operation is performed. 3. oe may be wired low to minimize the number of control signal s to the sram. the device will automatically turn off the output drivers during a write cycle. some users may use oe when the bus turn-on and turn-off times do not meet their requirements. 4. if an ignore clock edge command occurs dur ing a read operation, the i/o bus will re main active (low-z). if it occurs during a write cycle, the bus will remain in high-z. no write operations will be perfo rmed during the ignored clock edge cycle. 5. x means ?don?t care.? h means logic high. l means logic low. bwx = h means all byte write signals ( bw1 , bw2 , bw3 and bw4 ) are high. bwx = l means one or more byte write signals are low. 6. bw1 enables writes to byte ?a? (i/oa pins); bw2 enables writes to byte ?b? (i/ob pins); bw3 enables writes to byte ?c? (i/oc pins); bw4 enables writes to byte ?d? (i/od pins). 7. the address counter is incremented for all continue burst cycles.
a67l06181/A67L93361 (march, 2008, version 1.0) 9 amic technology, corp. partial truth table for read/write commands (x18) operation r/ w bw1 bw2 read h x x write byte ?a? l l h write byte ?b? l h l write all bytes l l l write abort/nop l h h note : using r/ w and byte write(s), any one or more bytes may be written. partial truth table for read/write commands (x36) operation r/ w bw1 bw2 bw3 bw4 read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h note : using r/ w and byte write(s), any one or more bytes may be written. linear burst address table (mode = low) first address (external) second a ddress (internal) third address (int ernal) fourth address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (mode = high or nc) first address (external) second a ddress (internal) third address (int ernal) fourth address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00
a67l06181/A67L93361 (march, 2008, version 1.0) 10 amic technology, corp. absolute maximum ratings* power supply voltage (vcc) . . . . . . . . . . -0.3v to +4.6v voltage relative to gnd for any pin except vcc (vin, vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc +0.3v commercial devices ( f ) operating temperature (topr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 70 c industrial devices ( i ) operating temperature (topr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 c to 85 c storage temperature (tbias) . . . . . . . . . . -10 c to 85 c storage temperature (tstg) . . . . . . . . . . -55 c to 125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics and operating conditions (0 c t a 70 c, -25 c t a 85 c, vcc, vccq = +3.3v 5% unless otherwise noted) symbol parameter conditions min. max. unit note v ih input high voltage 1.7 vcc+0.3 v 1,2 v il input low voltage -0.3 0.8 v 1,2 il i input leakage current 0v v ih vcc -2.0 4.0 a il o output leakage current output(s) disabled, 0v v in vcc -2.0 4.0 a v oh output high voltage i oh = -1.0ma 2.0 v 1,3 v ol output low voltage i ol = 1.0ma 0.4 v 1,3 vcc supply voltage 3.135 3.465 v 1 vccq isolated output buffer supply 3.135 vcc v 1,4 capacitance symbol parameter conditions typ. max. unit note c i control input capacitance 3 4 pf 6 c o input/output capacitance (i/o) 4 5 pf 6 c a address capacitance t a = 25 c; f = 1mhz vcc = 3.3v 3 3.5 pf 6 note : 1. all voltages referenced to vss (gnd). 2. overshoot : v ih +4.6v for t t khkh /2 for i 20ma undershoot : v il -0.7v for t t khkh /2 for i 20ma power-up : v ih +3.465v and vcc 3.135v for t 200ms 3. the load used for v oh , v ol testing is shown in figure 2. ac load cu rrent is higher than the shown dc values. ac i/o curves are available upon request. 4. vcc and vccq can be externally wir ed together to the same power supply. 5. this parameter is sampled.
a67l06181/A67L93361 (march, 2008, version 1.0) 11 amic technology, corp. i cc operating condition and maximum limits max. symbol parameter -6.5 -7.5 -8.5 unit conditions i cc power supply current : operating 460 440 410 ma device selected; all inputs v il or v ih ; cycle time t kc (min); vcc = max; output open i sb standby 80 80 80 ma device deselected; vcc = max; all inputs vss+0.2 or vcc-0.2; cycle time t kc (min) i sb1 standby 120 120 120 ma device deselected; vcc = max; all inputs vss+0.2 or vcc-0.2; all inputs static; clk frequency=max; zz v cc -0.2v i sb2 standby 70 70 70 ma device deselected; vcc = max; all inputs v il ; or v ih ; all inputs static; clk frequency=0 i sb2z sleep mode 70 70 70 ma zz v ih
a67l06181/A67L93361 (march, 2008, version 1.0) 12 amic technology, corp. ac characteristics (note 4) (0 c t a 70 c, -25 c t a 85 c, vcc, vccq = +3.3v 5% unless otherwise noted) -6.5 -7.5 -8.5 symbol parameter min. max. min. max. min. max. unit note clock t khkh clock cycle time 7.5 - 8.5 - 10 - ns t kf clock frequency - 133 - 117 - 100 mhz t khkl clock high time 2.5 - 2.8 - 3.0 - ns t klkh clock low time 2.5 - 2.8 - 3.0 - ns output times t khqv clock to output valid - 6.5 - 7.5 - 8.5 ns t khqx clock to output invalid 3.0 - 3.0 - 3.0 - ns t khqx1 clock to output in low-z 2.5 - 2.5 - 2.5 - ns 1,2,3 t khqz clock to output in high-z 1.5 3.8 1.5 4.0 1.5 5.0 ns 1,2,3 t glqv oe to output valid - 3.5 - 3.5 - 4.0 ns 4 t glqx oe to output in low-z 0 - 0 - 0 - ns 1,2,3 t ghqz oe to output in high-z - 3.5 - 3.5 - 4.0 ns 1,2,3 setup times t avkh address 1.5 - 2.0 - 2.0 - ns 5 t evkh clock enable ( cen ) 1.5 - 2.0 - 2.0 - ns 5 t cvkh control signals 1.5 - 2.0 - 2.0 - ns 5 t dvkh data-in 1.5 - 2.0 - 2.0 - ns 5 hold times t khax address 0.5 - 0.5 - 0.5 - ns 5 t khex clock enable ( cen ) 0.5 - 0.5 - 0.5 - ns 5 t khcx control signals 0.5 - 0.5 - 0.5 - ns 5 t khdx data-in 0.5 - 0.5 - 0.5 - ns 5 notes: 1. this parameter is sampled. 2. output loading is specified with c1=5pf as in figure 2. 3. transition is measured 200mv from steady state voltage. 4. oe can be considered a ?don?t care? during write; however, controlling oe can help fine-tune a system for turnaround timing. 5. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when adv/ ld is low and chip enabled. all other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk (when adv/ ld is low) to remain enabled.
a67l06181/A67L93361 (march, 2008, version 1.0) 13 amic technology, corp. ac test conditions input pulse levels gnd to 3.0v input rise and fall times 1.0ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 353 q +3.3v 319 5pf z o =50 q 50 v t =1.5v figure 1 output load equivalent figure 2 output load equivalent
a67l06181/A67L93361 (march, 2008, version 1.0) 14 amic technology, corp. sleep mode sleep mode is a low current ?power-down? mode in which the device is deselected and current is reduced to i sb2z . this duration of sleep mode is dictat ed by the length of time the zz is in a high state. afte r entering sleep mode, all inputs except zz become disabled and all outputs go to high-z. the zz pin is asynchronous, active high input that causes the device to enter sl eep mode. when the zz pin becomes logic high, isb2z is guaranteed after the time t zzi is met. any operation pending when entering sleep mode is not guaranteed to successfully complete. therefore, sleep mode (read or write) must not be initiated until valid pending operations are completed. similarly, when exiting sleep mode during t rzz , only a deselect or read cycle should be given while the sram is transitioning out of sleep mode. sleep mode electrical characteristics (vcc, vccq = +3.3v 5%) symbol parameter conditions min. max. unit note i sb2z current during sleep mode zz v ih - 70 ma t zz zz active to input ignored 0 2(t khkh ) ns 1 t rzz zz inactive to input sampled 0 2(t khkh ) ns 1 t zzi zz active to snooze current - 2(t khkh ) ns 1 t rzzi zz inactive to exit snooze current 0 ns 1 note : 1. this parameter is sampled. sleep mode waveform t rzz t zz t zzi i isb2z high-z deselect or read only output (q) all inputs (except zz) i supply zz clk : don't care t rzzi
a67l06181/A67L93361 (march, 2008, version 1.0) 15 amic technology, corp. read/write timing note : 1. for this waveform, zz is tied low. 2. burst sequence order is determined by mode (0 = linear, 1 = interleaved). brst operations are optional. 3. ce represents three signals. when ce = 0, it represents ce = 0, ce2 = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated the most current data is used. the most recent data may be from the input data register. a3 a2 a1 a4 a5 d(a1) write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect : don't care : undefined 12345 t khkh 678910 clk cen ce adv/ ld r/w bwx address i/o command a6 a7 d(a2) d(a2+1) oe t klkh t evk h t khe x t khkl t khcx t cvkh t khax t avkh t khdx t dvkh t khqv t khqx1 q(a3) t khqx t glqx t khqx t ghqz q(a6) d(a5) q(a4+1) t khqz t glqv q(a4) d(a7)
a67l06181/A67L93361 (march, 2008, version 1.0) 16 amic technology, corp. nop, stall and deselect cycles note : 1. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a ?pause.? a write is not performed during this cycle. 2. for this waveform, zz and oe are tied low. 3. ce represents three signals. when ce = 0, it represents ce = 0, 2 ce = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. a3 a2 a1 a4 a5 d(a4) q(a3) write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) deselect continue deselect : don't care : undefined 12345678910 clk cen ce adv/ ld r/w bwx address i/o command d(a1) q(a2) q(a5) t khqx t khqz
a67l06181/A67L93361 (march, 2008, version 1.0) 17 amic technology, corp. ordering information part no. configure cycle time / access time package a67l06181e-6.5if 7.5ns / 6.5ns 100l pb-free lqfp a67l06181e-6.5f 7.5ns / 6.5ns 100l pb-free lqfp a67l06181e-7.5if 8.5ns / 7.5ns 100l pb-free lqfp a67l06181e-7.5f 8.5ns / 7.5ns 100l pb-free lqfp a67l06181e-8.5if 10ns / 8.5ns 100l pb-free lqfp a67l06181e-8.5f 1m x 18 10ns / 8.5ns 100l pb-free lqfp A67L93361e-6.5if 7.5ns / 6.5ns 100l pb-free lqfp A67L93361e-6.5f 7.5ns / 6.5ns 100l pb-free lqfp A67L93361e-7.5if 8.5ns / 7.5ns 100l pb-free lqfp A67L93361e-7.5f 8.5ns / 7.5ns 100l pb-free lqfp A67L93361e-8.5if 10ns / 8.5ns 100l pb-free lqfp A67L93361e-8.5f 512k x 36 10ns / 8.5ns 100l pb-free lqfp note: -i is for industrial operating temperature range -25oc to +85oc.
a67l06181/A67L93361 (march, 2008, version 1.0) 18 amic technology, corp. package information lqfp 100l outline dimensions unit: inches/mm symbol dimensions in inches dimensions in mm min. nom. max. min. nom. max. a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.009 0.012 0.015 0.22 0.30 0.38 c 0.004 - 0.008 0.09 - 0.20 h e 0.866 bsc 22.00 bsc e 0.787 bsc 20.00 bsc h d 0.630 bsc 16.00 bsc d 0.551 bsc 14.00 bsc e 0.026 bsc 0.65 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref y - - 0.004 - - 0.10 0 3.5 7 0 3.5 7 notes: 1. dimensions d and e do not include mold protrusion. 2. dimensions b does not include dambar protrusion. total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 31 50 51 80 81 100 h d d e h e 130 b d y a 1 a 2 l 1 c e l

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